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[CIR][X86]Implement handling for convert-half builtins #173143

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[CIR][X86]Implement handling for convert-half builtins #173143

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0dd977d
Implement handling for convert-half builtins
Priyanshu3820 Dec 20, 2025
ed01553
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
50e380f
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
b238c17
Update CIRGenBuiltinsX86.cpp
Priyanshu3820 Dec 20, 2025
9d3a326
add support for maskz builtins
Priyanshu3820 Dec 20, 2025
d2118e6
Update CIRGenBuiltinX86.cpp
Priyanshu3820 Dec 20, 2025
4717d1c
Merge branch 'main' into x86-cvt-half-restart
Priyanshu3820 Dec 20, 2025
72d3ccc
Guard cast to cir::VectorType
Priyanshu3820 Dec 21, 2025
a37cef2
Update CIRGenBuiltinX86.cpp and test
Priyanshu3820 Dec 21, 2025
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22 changes: 21 additions & 1 deletion clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1831,9 +1831,29 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID, const CallExpr *expr) {
case X86::BI__builtin_ia32_vcvtph2ps_mask:
case X86::BI__builtin_ia32_vcvtph2ps256_mask:
case X86::BI__builtin_ia32_vcvtph2ps512_mask:
cgm.errorNYI(expr->getSourceRange(),
std::string("unimplemented X86 builtin call: ") +
getContext().BuiltinInfo.getName(builtinID));
return mlir::Value{};
case X86::BI__builtin_ia32_cvtneps2bf16_128_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_256_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_512_mask:
case X86::BI__builtin_ia32_cvtneps2bf16_512_mask: {
mlir::Location loc = getLoc(expr->getExprLoc());
cir::VectorType resTy = cast<cir::VectorType>(convertType(expr->getType()));
unsigned numElts = resTy.getSize();
StringRef intrinsicName;
if (builtinID == X86::BI__builtin_ia32_cvtneps2bf16_128_mask)
intrinsicName = "x86.avx512bf16.cvtneps2bf16.128";
else if (builtinID == X86::BI__builtin_ia32_cvtneps2bf16_256_mask)
intrinsicName = "x86.avx512bf16.cvtneps2bf16.256";
else
intrinsicName = "x86.avx512bf16.cvtneps2bf16.512";
mlir::Value selectMask = getMaskVecValue(builder, loc, ops[2], numElts);
mlir::Value intrinsicResult = emitIntrinsicCallOp(
builder, loc, intrinsicName, resTy, mlir::ValueRange{ops[0]});
return emitX86Select(builder, loc, selectMask, intrinsicResult, ops[1]);
}

case X86::BI__cpuid:
case X86::BI__cpuidex:
case X86::BI__emul:
Expand Down
44 changes: 44 additions & 0 deletions clang/test/CIR/CodeGenBuiltins/X86/avx512vlbf16-builtins.c
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@@ -0,0 +1,44 @@
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -fclangir -emit-cir -o %t.cir -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -fclangir -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefixes=LLVM --input-file=%t.ll %s
// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +avx512f -target-feature +avx512vl -target-feature +avx512bf16 -emit-llvm -o %t.ll -Wall -Werror -Wsign-conversion
// RUN: FileCheck --check-prefixes=OGCG --input-file=%t.ll %s

#include <immintrin.h>

__m256bh test_mm512_mask_cvtneps_pbh(__m256bh src, __mmask16 k, __m512 a) {
// CIR-LABEL: @test_mm512_mask_cvtneps_pbh
// CIR: cir.call @_mm512_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<16 x !cir.bf16>, !u16i, !cir.vector<16 x !cir.float>) -> !cir.vector<16 x !cir.bf16>

// LLVM-LABEL: @test_mm512_mask_cvtneps_pbh
// LLVM: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512

// OGCG-LABEL: @test_mm512_mask_cvtneps_pbh
// OGCG: call <16 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.512
return _mm512_mask_cvtneps_pbh(src, k, a);
}

__m128bh test_mm256_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m256 a) {
// CIR-LABEL: test_mm256_mask_cvtneps_pbh
// CIR: cir.call @_mm256_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<8 x !cir.float>) -> !cir.vector<8 x !cir.bf16>

// LLVM-LABEL: test_mm256_mask_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})

// OGCG-LABEL: test_mm256_mask_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.cvtneps2bf16.256(<8 x float> {{.+}})
return _mm256_mask_cvtneps_pbh(src, k, a);
}

__m128bh test_mm_mask_cvtneps_pbh(__m128bh src, __mmask8 k, __m128 a) {
// CIR-LABEL: test_mm_mask_cvtneps_pbh
// CIR: cir.call @_mm_mask_cvtneps_pbh({{.+}}, {{.+}}, {{.+}}) : (!cir.vector<8 x !cir.bf16>, !u8i, !cir.vector<4 x !cir.float>) -> !cir.vector<8 x !cir.bf1{{.+}}

// LLVM-LABEL: test_mm_mask_cvtneps_pbh
// LLVM: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> %extract.i)

// OGCG-LABEL: test_mm_mask_cvtneps_pbh
// OGCG: call <8 x bfloat> @llvm.x86.avx512bf16.mask.cvtneps2bf16.128(<4 x float> {{.+}}, <8 x bfloat> {{.+}}, <4 x i1> %extract.i)
return _mm_mask_cvtneps_pbh(src, k, a);
}
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